Addressing circuit

ABSTRACT

A transformer-coupled memory addressing circuit uses first and second groups of addressing transformers with each addressing input being applied to the primary winding of one of the transformers of the first group and all but one of the primary windings of the second group. Each primary winding of each transformer of the first group links a plurality of secondary windings equal in number to the number of transformers in the second group. Each of these secondaries of the first group then is connected in series with an oppositely-wound secondary from a different transformer in the second group, so that only when a secondary winding of the first group has current induced in it in the absence of current induced in its series-connected winding of the second group is the desired output obtained for a particular address.

I United States Patent 1 3,576,434

[72] .lnventor Alfons Reszka 3,159,828 12/1964 Davis et a1. 340/347 Northbrook, 111. 3,287,700 11/1966 Flowers 340/166 [2]] App]. No. 707,532 3,418,460 12/1968 Clemson 340/347X [22] Flled 1968 Primary ExaminerThomas A. Robinson [45] Patented 1971 Assistant Examiner-Gary R Edwards [73] Assgnee f fi Alt0rneys-T. L. Landis and R. P. Miller [54] ADDRESSING CIRCUIT ABSTRACT: A transformer-coupled memory addressing cir- 9 Claims, 1 Drawing Fig cuit uses first and second groups of addressing transformers with each addressing input being applied to the primary wind- [52] U.S. Cl 235/154, ing f one f h transformers of the first group and all but one 340/347 of the primary windings of the second group. Each primary [51 I [1!!- Cl H03k13/247 i ding of each transformer of [he first group links a plurality [50] Field of Search 340/166, f secondary windings equal in number to the number f 347; 235/154 transformers in the second group. Each of these secondaries of the first group then is connected in series with an opposite- [56] References cued ly-wound secondary from a different transformer in the UNITED STATES PATENTS second group, so that only when a secondary winding of the 2,734,183 2/ 1956 Rajchman 340/ 166 first group has current induced in it in the absence of current 2,920,317 1 1960 Mallery 340/347 induced in its series-connected winding of the second group is 2,964,737 12/ 1960 Christopherson 340/347X the desired output obtained for a particular address.

Patented April 27, 1971 DECODER ADDRESSING CIRCUIT BACKGROUND OF THE INVENTION In electronic data processing systems there are many applications for read-only memories in which the storage of information is relatively fixed by the configuration and construction of the memory and where the storedinformation can be read out of the memory as frequently as is desired without destroying the stored information. One type of read-only memory, which permits the convenient substitution of words stored in the memory, uses transformer coupled inputs and outputs wherein the primary windings of the transformers are on printed winding sheets which are selectively encoded with the memory infonnation and placed over the cores of the transformers. Each of the primary winding sheets is encoded to represent a different word of character, and whenever a particular primary winding sheet is supplied with an input signal, a signal corresponding to this word or character is induced in the secondary windings of the transformers and may be utilized by any suitable device connected to the output of the memory.

Generally, the windings are printed on a sheet of insulating material of a suitable plastic, such as Mylar," and it has been necessary to connect the end terminals of the primary winding conductor sheets to the input signal source by means of direct electrical connections. Thus, when a sheet is replaced in order to change the information stored in the memory, it is necessary to sever these connections and to make new connections with a newly inserted sheet bearing the new information placed in the memory. In addition, an input amplifier generally is required for each of the primary winding sheets in a direct-wired memory of this type; so that if the memory is utilized to decode a large number of words, a correspondingly large number of input amplifiers are required.

SUMMARY OF THE INVENTION In accordance with a preferred embodiment of this invention, the addressing circuit for the printed primary windings of a plurality of memory transformers consists of first and second groups of addressing transformers with each addressing input being applied to the primary winding of one of the transformers of the first group and being applied to all but one of the primary winding of the second group. Each primary winding of each transformer of the first group links a plurality of secondary windings equal in number to the number of transformers in the second group. Each of the secondary windings of the first group then is connected in series with a secondary winding from a different transformer in the second group, and the windings are arranged such that current induced in the secondary windings of the first group opposes current induced in secondary windings of the second group. Each set of seriesconnected windings then is connected to the end terminals of the printed primary windings of a different primary winding sheet in the memory transformers. This can be accomplished by printing the series-connected secondaries on the same sheets as the primary windings of the memory transformers. Only when a secondary winding of the first group has current induced in it, in the absence of current induced in its seriesconnected winding of the second group, does current flow through the printed primary winding of the corresponding sheet in the memory transformer. v I

BRIEF DESCRIPTION OF THE DRAWING The single FIGURE of the drawing is a schematic diagram of an addressing circuit made in accordance with a preferred embodiment of the invention.

DETAILED DESCRIPTION Referring now to the drawing, there is shown an addressing circuit in which the input signals for effecting the selection of a particular address in a read-only memory are supplied to a -decoder circuit 10, which may be of anysuitable type; such as a circuit for converting permutation-coded input signals to digital output signals. For the purpose of illustration, assume that the decoder circuit 10 is capable of providing 25 difierent digital outputs in response to input signals supplied to it. These 25 digital outputs are supplied on 25 output leads 11 with only a single output signal being obtained from the decoder 10 at any one time. Each output lead 11 then is connected to one input of a first group of five input OR gates 12a to l2e. Thus, there are 25 inputs to the OR gates 12, each input being connected to a different one of the outputs of the decoder 11. In the drawing, only two of these inputs are shown connected to output leads Ila and 11b in order to avoid unnecessary cluttering o-f the drawing. The outputs on leads I] from the decoder 10 also are supplied through a blocking diode 13 to the inputs of four out of a second group of five four-input OR gates 14a to Me. For the purpose of illustration, the output lead 11a is shown as being connected to the inputs of the four OR gates 14a to 14d, while the output lead 11b is shown as being connected to the inputs of the OR gates 14a through 14c and 14e. Both of the outputs 11a and 11b, however, are connected to the inputs of the OR gate 12a. While the OR gates 14 are shown for simplicity with only four inputs each, it will be evident that each amplifier 16 must be energizable by no less than 20 different ones of the 25 output leads 11. To accomplish this, five OR gates can be used with each amplifier l6-rather than the one OR gate 14 that is shown for simplicity in the drawing. Alternatively, each OR gate 14 could be provided with 20 inputs. As still another alternative, the 25 diodes 13 could be considered as being arranged as five OR gates, each such five-input OR gates having five diodes l3 driving four of the OR gates 14.

The OR gates l6ana 14 edntrol the input bias supplied to two groups of amplifiers I5 and I 6, respectively, indicated in the drawing as NPN transistors, with amplifiers ISa-through I5e being controlled by the outputs of the OR gates 12a through I2e, respectively, and with amplifiers 16a through l6e being controlled by the outputs of the OR gates 14a through He, respectively. Normally, in the absence of an output signal from the respective OR gates 12 and 14, the transistors 15 and 16 are nonconductive, so that no current flows through them. The collector of each of the transistors 1511 through l5e is connected through a current limiting resistor 17a through 17e to the primary (first) winding of a corresponding one of a first group of addressing transformers 18a through 18e. Only the transformer 18a has been shown in detail, but all of the transformers 18 are identical, having a single primary winding and five secondary (second) windings. Similarly, the collectors of the transistors 16a through l6e are connected through current limiting resistors 20a through 20e to the primary windings of a second group of addressing transformers 22a through 22e. The transformers 22 are identical to the transformers 18, each having a single primary winding and five secondary windings. Only the transformer 22e has been shown in detail, but all of the transformers 22 are identical. Current for energizing the primary windings of the transformers l8 and 22 is supplied by a battery 19 which is connected in series with each primary winding, the associated current limiting resistor 17 or 20 and the transistor amplifier 15 or 16 for each of the addressing transformers 18 or 22.

Each of the secondary windings of the transformer 18a is connected in series with the secondary windings of a different one of the transformers 22 and, as shown in the drawing, the upper secondary winding of the transformer 18a is connected in series with a secondary winding of the transformer 22e while the next lower secondary winding of the transformer 18a is connected in series with a secondary winding of the transformer 22d. Each set of series-connected secondary windings from the transformers l8 and 22 is connected to the input terminals 50 and 52 of a different one of a plurality of primary winding sheets 36 fitted over a plurality of memory transformers (not shown). This connection is made through a diode 23 so that current pulses flowing in one direction only pass through the printed primary windings on the sheets 36.

In order to select a particular one of the printed primary winding sheets 36 in preference to all other sheets, one of the output leads 11 from the decoder is energized. For the purpose of illustration, assume that this output lead is the output lead 11a. As a result, a signal is passed by the OR gate 120 to render the transistor a conductive, which results in a pulse of current flowing through the primary winding of the transformer 18a. This induces a current pulse in all five of the secondary windings on the addressing transformer 18a flowing in the direction of the diodes 23 which are connected in series with the secondary windings of the transformer 18a. The cur rent pulses induced in the four secondary windings corresponding to the printed primary winding sheets 36 which are not to be selected must be suppressed. This is accomplished by the series-connections between the secondary windings on the transformers 18 with corresponding secondary windings on the transformers 22.

As stated previously, each of the secondary windings from the transformer 18a is connected in series with a secondary winding on a different one of the transformers 22a through 2242 with the upper secondary windings on the transformer 18a being connected in series with the upper secondary winding of the transformer 22e. All of the other secondary windings of the transformer 18a are connected to a secondary winding on the transformers 22a through 22d respectively. At the same time that a signal is passed by the OR gate 12a to render the transistor amplifier 15a conductive, a signal also is passed through a diode 13 to each of the OR gates 14a, 14b, 14c and 14d to render the transistor amplifiers 16a through 16d conductive. It should be noted, however, that no signal is applied over lead 11a to the OR gate Me, so that the transistor amplifier l6e remains nonconductive at this time. Since the primary winding of the addressing transformer 22a connected to the output of the transistor amplifier 16a is not energized at this time, there is no current pulse induced in any of the secondary windings of the transformer 222. Thus, current flows from the upper secondary winding of the transformer 18a, .through the diode 23 to the terminal 52, through the printed primary winding on the top printed primary winding sheet 36 to the terminal 50, through the upper secondary winding of the transformer 22c and back to the upper secondary winding of the transformer 18a.

At the same time, current flows into the primary windings of each of the transformers 2211 through 22d causing a current pulse to be induced in all of the secondary windings of these transformers. It should be noted that the primary windings of .the transformers 22 are supplied with current flowing in a direction opposite to the current supplied to the primary windings of the transformers 18. As a result, the current pulses induced in the secondary windings of transformers 22a to 22d are in opposition to the current induced in the secondary windings of the transformer 18a. The amplifiers l5 and 16 and the transformers l8 and 22 are chosen so that the currents induced in the secondary windings of the transformers l8 and 22 are of equal magnitude, which causes the current induced in the secondary windings of the transformers 220 through 22d to cancel the current induced in the secondary windings of the transformer 18a connected in series therewith, since theses currents are equal and opposite. Thus, no current flows through the diodes 23 connected to the lower four secondary windings of the transformer 184 when the lead 11a provides an output pulse from the decoder 10. The diodes 23 also prevent any current from flowing through the printed primary winding on any of the sheets 36 due to a voltage pulse being induced in a secondary winding on any of the transformers 22 in the absence of a voltage pulse being induced in a corresponding secondary winding of one of the transformers 18a through l8e. This causes only the top memory sheet 36 to be provided with an input current in response to the selected one of the 25 outputs of the decoder 10 supplied over the lead 11a.

A similar selection of the next sheet 36 from the top sheet 36 is effected by the provision of an output pulse on the lead 22b, 22c and 22a to be energized; so that only the transformer 22d does not provide a blocking signal to the secondary winding of the transfonner connected in series with a secondary winding thereof. As a result, only the second from the top sheet 36 is selected by an input signal on the lead 111:. A similar showing could be made for each of the 25 outputs of the decoder 10. It should be noted that the first five of these outputs cause current to flow in the primary winding of the transformer 18a coupled with the absence of current in the primary winding of a different one of each of the five transformers in the group of transformers 22a through 22e. Similarly, the next five outputs of the decoder 10 cause current to flow in the primary winding of the transformer 18b, with corresponding lack of current in the primary winding of a dif ferent one of the transformers 220 through 22a for each of the five different inputs to the OR gate 12b. The diodes 13 are necessary to prevent the feed back of signals to the OR gates 12a to He from the application of signals to the inputs of the OR gates 14a through Me.

The printed primary winding sheets 36 used as the output utilization devices for the memory addressing circuit may include printed thereon the secondary windings of the corresponding transformers 18 and 22 which are used to select a particular sheet 36. Then the different sheets 36 using these secondary winding inputs printed thereon, may be slipped over the appropriate transformer cores 18 and 22 so that no direct wiring directions to the terminals 50 and 52 are required. Thus, in order to decode the 25 inputs shown in the embodiment of the drawing, each transformer 18a would have five sheets 36 with a corresponding secondary winding threaded through the core of the transformer 18a and a seriesconnected secondary winding on each of the different sheets selectively threaded through a different core of the group of transformers 22a through 22e. Similarly, the five sheets having secondary windings from the transformer 18b and the five sheets from the transformer 180; etc., would have series-connected secondary windings selectively threaded through the cores of the transformers 22a through 22e. In addition, the transformer-coupled memory addressing circuit disclosed in the preferred embodiment of this invention also may be used to address any type of read-only memory and is not limited to addressing of a read-only memory using printed primary winding sheets of the type disclosed in the preferred embodiment.

By dividing the addressing transformers into two groups with series-connected secondary windings, it is possible to substantially reduce the number of input amplifiers needed to select the memory address positions, with 10 amplifiers and IO-addressing transformers being capable of selecting any one of 25-memory address locations; and with 16 amplifiers and l6-addressing transformers being capable of selecting any one of 64 possible address positions in a read-only memory. It also should be noted that it is not necessary to have an equal number of addressing transformers and amplifiers in each group. The best utilization of the addressing transformers, however, results when this number is equal since the maximum possible number of address outputs for a given number of addressing transformers is realized when the two groups of addressing transformers 18 and 22 are equal in number.

Although a particular embodiment of the invention is shown in the drawing and has been described in the foregoing specification, it is to be understood that other modifications of this addressing circuit, varied to fit particular operating conditions, will be apparent to those skilled in the art; and the invention is not to be considered limited to the embodiment chosen for purposes of disclosure, and covers all changes and modifications which do not constitute departures from the true scope of the invention.

lclaim:

1. An addressing circuit including:

a first transformer having a primary winding and a plurality of secondary windings for producing an output signal on all of said secondary windings in response to receipt of a signal on the primary winding;

a plurality of second transformers each having a primary winding and a plurality of secondary windings for producing an output signal in response to input signals applied to their primary windings;

means for combining each of the secondary windings of the first transfonner with a secondary winding of a different one of the second transformers for producing a single output signal indicative of the desired address; and

means for supplying an input signal to the primary winding of the first transformer and to the primary windings of all but one of the second transformers.

2. A circuit according to claim 1 wherein the combining means comprises a series-connection of each secondary winding of the first transformer with a secondary winding of a different second transfonner.

3. A circuit according to claim 2 wherein the currents induced in the secondary windings of the first and second transformers are of substantially equal magnitude and wherein the current induced in the secondary windings of the first transformer opposes the current induced in the secondary windings of the second transformers.

4. A circuit according to claim I wherein the presence of an output signal from a secondary winding of one of the second transformers inhibits the output signal from the secondary winding of the first transformer with which it is combined by the combining means.

5. An addressing circuit including:

a first group of transformers, each having a first winding and a plurality of second windings;

a second group of transfonners, each having a first winding and a plurality of second windings;

means for connecting each of the second windings of each transformer of the first group of transformers in series with a second winding from a different one of the transformers of the second group of transformers, said seriesconnected second windings being adapted for connection to a load; and

means for simultaneously energizing the first winding of one transformer in the first group of transformers and all but one of the first windings of the transformers in the second group of transformers.

6. A circuit according to claim 5 wherein the current induced in the second windings of the first group of transfonners opposes the current induced in the second windings of the second group of transformers.

7. A circuit according to claim 6 wherein the currents induced in the second windings of both groups of transfonners are of substantially equal magnitude.

8. A circuit according to claim 5 having an output conductor for each of said series-connected second windings wherein a desired output indication is obtained from only when current is induced in the second winding from the first group of transformers in the absence of any current being induced in the series-connected winding from the second group of transformers.

9. A circuit according to claim 5 wherein the number of transformers in the first group of transformers is equal to the number of transformers in the second group of transformers. 

1. An addressing circuit including: a first transformer having a primary winding and a plurality of secondary windings for producing an output signal on all of said secondary windings in response to receipt of a signal on the primary winding; a plurality of second transformers each having a primary winding and a plurality of secondary windings for producing an output signal in response to input signals applied to their primary windings; means for combining each of the secondary windings of the first transformer with a secondary winding of a different one of the second transformers for producing a single output signal indicative of the desired address; and means for supplying an input signal to the primary winding of the first transformer and to the primary windings of all but one of the second transformers.
 2. A circuit according to claim 1 wherein the combining means comprises a series-connection of each secondary winding of the first transformer with a secondary winding of a different second transformer.
 3. A circuit according to claim 2 wherein the currents induced in the secondary windings of the first and second transformers are of substantially equal magnitude and wheRein the current induced in the secondary windings of the first transformer opposes the current induced in the secondary windings of the second transformers.
 4. A circuit according to claim 1 wherein the presence of an output signal from a secondary winding of one of the second transformers inhibits the output signal from the secondary winding of the first transformer with which it is combined by the combining means.
 5. An addressing circuit including: a first group of transformers, each having a first winding and a plurality of second windings; a second group of transformers, each having a first winding and a plurality of second windings; means for connecting each of the second windings of each transformer of the first group of transformers in series with a second winding from a different one of the transformers of the second group of transformers, said series-connected second windings being adapted for connection to a load; and means for simultaneously energizing the first winding of one transformer in the first group of transformers and all but one of the first windings of the transformers in the second group of transformers.
 6. A circuit according to claim 5 wherein the current induced in the second windings of the first group of transformers opposes the current induced in the second windings of the second group of transformers.
 7. A circuit according to claim 6 wherein the currents induced in the second windings of both groups of transformers are of substantially equal magnitude.
 8. A circuit according to claim 5 having an output conductor for each of said series-connected second windings wherein a desired output indication is obtained from only when current is induced in the second winding from the first group of transformers in the absence of any current being induced in the series-connected winding from the second group of transformers.
 9. A circuit according to claim 5 wherein the number of transformers in the first group of transformers is equal to the number of transformers in the second group of transformers. 